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Preliminary Technical Data
FEATURES
AD7798: 16-Bit AD7799: 24-Bit Three Differential Analog Inputs Low Noise Programmable Gain Amp RMS noise: 80 nV (Gain = 64) at 16.6 Hz update rate (AD7798) 65 nV (Gain = 64) at 16.6 Hz update rate (AD7799) 30 nV (Gain = 64) at 4 Hz update rate (AD7799) Update Rate: 4 Hz to 500 Hz Power Supply: 2.7 V to 5.25 V operation Normal: 330 A typ (AD7798) 400 A typ (AD7799) Power-down: 1 A max Simultaneous 50 Hz/60 Hz Rejection Two Programmable Digital Outputs Internal Clock Oscillator Reference Detect 100 nA Burnout Currents Low Side Power Switch Independent Interface Power Supply 16-Lead TSSOP Resolution:
Low Power, 24-Bit/16-Bit Sigma-Delta ADC with In-Amp AD7798/AD7799
FUNCTIONAL BLOCK DIAGRAM
AD7799/AD7798
AVDD AIN1(+) AIN1(-) AIN2(+) AIN2(-) AIN3(+)/P1 AIN3(-)/P2 PWRSW GND REFERENCE DETECT
MUX
IN-AMP
SIGMA DELTA ADC
SERIAL INTERFACE AND CONTROL LOGIC
DOUT/RDY DIN SCLK CS
GND
INTERNAL CLOCK
DVDD
Figure 1.
GENERAL DESCRIPTION
The AD7798/AD7799 is a low power, complete analog front end for low frequency measurement applications. The device contains a low noise 24-bit (AD7799)/ 16-bit (AD7798) - ADC with three differential inputs. The on-chip low noise instrumentation amplifier means that signals of small amplitude can be interfaced directly to the ADC. With a gain setting of 64, the rms noise is 80 nV for AD7798 and 65 nV for the AD7799 at 16.6 Hz. The device contains a low side power switch which is useful in bridge applications. The switch allows the bridge to be disconnected from the power supply when conversions are not being performed and this will minimise power consumption. The device also has 100 nA burnout currents. These currents are used to detect if sensors connected to the analog inputs are burnt out. Other on-chip features include an internal clock so the user does not have to supply a clock to the device. This reduces the component count in a system and provides board space savings. The update rate is programmable on the AD7798/99. It can be varied from 4 Hz to 500 Hz. The part operates with a single power supply from 2.7 V to 5.25 V. It consumes a current of 380 uA maximum for the AD7798 and 450 uA maximum for the AD7799. The AD7799/AD7798 is housed in a 16-lead TSSOP package.
INTERFACE
3-wire serial SPI(R), QSPITM, MICROWIRETM, and DSP compatible Schmitt trigger on SCLK
APPLICATIONS
Pressure measurement Weigh scales
Rev. PrD.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD7798/AD7799 TABLE OF CONTENTS
AD7799/AD7798--Specifications.................................................. 3 Timing Characteristics, .................................................................... 6 Absolute Maximum Ratings............................................................ 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 On-chip Registers ........................................................................... 12 Communications Register (RS2, RS1, RS0 = 0, 0, 0) .............. 12 Status Register (RS2, RS1, RS0 = 0, 0, 0; Power-on/Reset = 0x88)............................................................................................. 13 Mode Register (RS2, RS1, RS0 = 0, 0, 1; Power-on/Reset = 0x000A)........................................................................................ 13
Preliminary Technical Data
Configuration Register (rs2, RS1, RS0 = 0, 1, 0; Poweron/Reset = 0x0710) .................................................................... 15 Data Register (RS2, RS1, RS0 = 0, 1, 1; Power-on/Reset = 0x0000 (AD7798)/ 0x000000 (AD7799))................................ 16 ID Register (RS2, RS1, RS0 = 1, 0, 0; Power-on/Reset = 0xX8 (AD7798)/ 0xX9 (AD7799))..................................................... 16 OFFSET Register (RS2, RS1, RS0 = 1, 1, 0; Power-on/Reset = 0x8000 (AD7798)/0x800000 (AD7799))................................. 17 FULLSCALE Register (RS2, RS1, RS0 = 1, 1, 1; Poweron/Reset = 0x5XXX (AD7798)/0x5XXX000 (AD7799)) ..... 17 TYPICAL APPLICATION........................................................ 17
REVISION HISTORY
Prelim D, June 2004: Initial Version
REV. PrD. Page 2 of 17
Preliminary Technical Data AD7799/AD7798--SPECIFICATIONS1
AD7798/AD7799
Table 1. (AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; REFIN(+) = 2.5 V; REFIN(-) = 0 V; all specifications TMIN to TMAX, unless otherwise noted.)
Parameter ADC CHANNEL SPECIFICATION Output Update Rate ADC CHANNEL No Missing Codes2 Resolution AD7798/AD7799B 4 500 24 16 16 19 16 18.5 See Tables in ADC Description 15 25 3 10 10 0.5 3 90 REFIN/Gain GND + 30 mV AVDD - 30 mV GND + 100 mV AVDD - 100 mV GND + 300 mV VDD - 1.2 0.5 Unit Hz min nom Hz max nom Bits min Bits min Bits p-p Bits p-p Bits p-p Bits p-p AD7799, fADC 125 Hz AD7798 Gain = 128, 16.6 Hz Update Rate Gain = 1, 16.6 Hz Update Rate, AD7799 Gain = 1, 16.6 Hz Update Rate, AD7798 Gain = 64, 4 Hz Update Rate, AD7799 Test Conditions/Comments
Output Noise and Update Rates Integral Nonlinearity Offset Error3 Offset Error Drift vs. Temperature4 Full-Scale Error5 Gain Drift vs. Temperature4 Power Supply Rejection ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Unbuffered Mode Buffered Mode In-Amp Enabled Common Mode Voltage In-Amp Enabled Analog Input Current Buffered Mode or In-Amp Enabled Average Input Current
2
ppm of FSR max ppm of FSR max V typ nV/C typ V typ ppm/C typ ppm/C typ dB min V nom V max V min V min V max V min V max V min
3.5 ppm typ, Gain 1 to 32 Gain = 64 or 128
Gain = 1, 2 Gain = 4 to 128 100 dB typ, AIN = 50 % of full scale REFIN = REFIN(+) - REFIN(-), Gain = 1 to 128 Gain = 1 or 2 Gain = 1 or 2 Gain = 4 to 128
Gain = 4 to 128
Average Input Current Drift Unbuffered Mode Average Input Current Average Input Current Drift Normal Mode Rejection2 @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz Common Mode Rejection @DC @ 50 Hz, 60 Hz
2
200 1 2 400 50 70 84 90 90 100
pA max nA max pA/C typ nA/V typ pA/V/C typ dB min dB min dB min dB min dB min
AIN1(+) - AIN1(-), AIN2(+) - AIN2(-) only. AIN3(+) - AIN3(-). Gain = 1 or 2 Input current varies with input voltage.
73 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 10106 90 dB typ, 50 1 Hz, FS[3:0] = 10016 90 dB typ, 60 1 Hz, FS[3:0] = 10006 AIN = 50% of FS 80 dB typ, FS[3:0] = 10106 50 1 Hz (FS[3:0] = 10016), 60 1 Hz (FS[3:0] = 10006)
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AD7798/AD7799
Parameter REFERENCE INPUT REFIN Voltage Reference Voltage Range AD7798/AD7799B 2.5 0.1 AV DD GND - 30 mV AVDD + 30 mV 400 0.03 See ANALOG INPUTS See ANALOG INPUTS 0.3 0.65 5 7 20 64 2% 0.01 Unit V nom V min V max V min V max nA/V typ nA/V/C typ
Preliminary Technical Data
Test Conditions/Comments REFIN = REFIN(+) - REFIN(-)
2
Absolute REFIN Voltage Limits
2
Average reference Input Current Average Reference Input Current Drift Normal Mode Rejection Common Mode Rejection Reference Detect
2
V min V max max max mA max KHz nom %/C typ
NOREF bit Inactive if VREF < 0.3 V NOREF bit Active if VREF > 0.65 V AVDD = 5V AVDD = 3V Continuous Current
LOW SIDE POWER SWITCH RON Allowable Current INTERNAL CLOCK Drift LOGIC INPUTS All Inputs Except SCLK and DIN VINL, Input Low Voltage VINH, Input High Voltage SCLK and DIN Only (SchmittTriggered Input) VT(+) VT(-) VT(+) - VT(-) VT(+) VT(-) VT(+) - VT(-) Input Currents Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage VOH, Output High Voltage VOL, Output Low Voltage
2 2 2 2 2
0.8 0.4 2.0
V max V max V min
DVDD = 5 V DVDD = 3 V DVDD = 3 V or 5 V
1.4/2 0.8/1.4 0.3/0.85 0.9/2 0.4/1.1 0.3/0.85 1 10 DVDD - 0.6 0.4 4 0.4 1 10 Offset Binary
V min/V max V min/V max V min/V max V min/V max V min/V max V min/V max A max pF typ V min V max V min V max A max pF typ
DVDD = 5 V DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 3 V VIN = DVDD or GND All Digital Inputs DVDD = 3 V, ISOURCE = 100 A DVDD = 3 V, ISINK = 100 A DVDD = 5 V, ISOURCE = 200 A DVDD = 5 V, ISINK = 1.6 mA
Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding DIGITAL OUTPUTS P1 and P2 VOH, Output High Voltage2 VOL, Output Low Voltage VOH, Output High Voltage2 VOL, Output Low Voltage
2 2
AVDD - 0.6 0.4 4 0.4
V min V max V min V max
AVDD = 3 V, ISOURCE = 100 A AVDD = 3 V, ISINK = 100 A AVDD = 5 V, ISOURCE = 200 A AVDD = 5 V, ISINK = 800 A
REV. PrD. Page 4 of 17
Preliminary Technical Data
Parameter SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span AD7798/AD7799B 1.05 x FS -1.05 x FS 0.8 x FS 2.1 x FS Unit V max V min V min V max
AD7798/AD7799
Test Conditions/Comments
POWER REQUIREMENTS7 Power Supply Voltage VDD - GND IOVDD - GND Power Supply Currents IDD Current
2.7/5.25 2.7/5.25 150 175 380 450 1
V min/max V min/max A max A max A max A max A max 125 A typ, Unbuffered Mode 150 A typ, Buffered Mode, In-Amp Bypassed 330 A typ, In-Amp used (AD7798) 400 A typ, IN-AMP used (AD7799)
IDD (Power-Down Mode)
1 2 3
Temperature Range -40C to +105C. Specification is not production tested but is supported by characterization data at initial product release. A System calibration will reduce this error to the order of the noise for the programmed gain and update rate. 4 A calibration at any temperature will remove this error. 5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V). 6 FS[3:0] are the four bits used in the mode register to select the output word rate. 7 Digital inputs equal to DVDD or GND.
REV. PrD. Page 5 of 17
AD7798/AD7799 TIMING CHARACTERISTICS8, 9
Preliminary Technical Data
Table 2. (AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.)
Parameter t3 t4 Read Operation t1 Limit at TMIN, TMAX (B Version) 100 100 0 60 80 0 60 80 10 80 100 10 0 30 25 0 Unit ns min ns min ns min ns max ns max ns min ns max ns max ns min ns max ns max ns min ns min ns min ns min ns min Conditions/Comments SCLK High Pulsewidth SCLK Low Pulsewidth CS Falling Edge to DOUT/RDY Active Time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK Active Edge to Data Valid Delay11 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus Relinquish Time after CS Inactive Edge SCLK Inactive Edge to CS Inactive Edge SCLK Inactive Edge to DOUT/RDY High CS Falling Edge to SCLK Active Edge Setup Time Data Valid to SCLK Edge Setup Time Data Valid to SCLK Edge Hold Time CS Rising Edge to SCLK Edge Hold Time
11
t210
t512, 13 t6 t7 Write Operation t8 t9 t10 t11
8 9
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 3 and Figure 4. These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. SCLK active edge is falling edge of SCLK.
10
11
12
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
13
RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.
REV. PrD. Page 6 of 17
Preliminary Technical Data
AD7798/AD7799
TO OUTPUT PIN +1.6 V 50 pF
Figure 2. Load Circuit for Timing Characterization
CS (I)
t1
DOUT/RDY (O) MSB LSB
t6 t5
t2 t3
SCLK (I)
t7
t4
I = INPUT, O = OUTPUT
04227-0-003
Figure 3. Read Cycle Timing Diagram
CS (I)
t8
SCLK (I)
t11
t9 t10
DIN (I) MSB LSB
04227-0-004
I = INPUT, O = OUTPUT
Figure 4. Write Cycle Timing Diagram
REV. PrD. Page 7 of 17
AD7798/AD7799 ABSOLUTE MAXIMUM RATINGS
Table 3. (TA= 25C, unless otherwise noted.)
Parameter AVDD to GND DVDD to GND Analog Input Voltage to GND Reference Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND AIN/digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature TSSOP JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared Rating -0.3V to +7V -0.3V to +7V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to DVDD + 0.3 V 10 mA -40C to +105C -65C to +150C 150C 97.9C/W 14C/W 215C 220C
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
REV. PrD. Page 8 of 17
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCLK CS
1 2 16 15 14
AD7798/AD7799
DIN D OU T /RD Y D VD D AV D D GND PWRSW REFI N(- ) REFI N(+ )
AI N3(+)/P1 3 AI N3(- )/P2 AI N1(+) AI N1(- ) AI N2( +) AI N2(- )
4 5 6 7 8
AD 7799/98
T OP VI EW (Not To Scale)
13 12 11 10 9
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 Mnemonic SCLK Function Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. Analog Input/Digital Output pin. AIN3(+) is the positive terminal of the differential analog input pair AIN3(+)/AIN3(-). Alternatively, this pin can function as a general purpose output bit referenced between AVDD and GND Analog Input/ Digital Output pin. AIN3(-) is the negative terminal of the differential analog input pair AIN3(+)/AIN3(-). Alternatively, this pin can function as a general purpose output bit referenced between AVDD and GND Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(-). Analog Input. AIN1(-) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(-). Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(-). Analog Input. AIN2(-) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(-). Positive Reference Input. REFIN(+) can lie anywhere between AVDD and GND + 0.1 V. The nominal reference voltage (REFIN(+) - REFIN(-)) is 2.5 V, but the part functions with a reference from 0.1 V to AVDD. Negative Reference Input. This reference input can lie anywhere between GND and AVDD - 0.1 V. Low Side Power Switch to GND. Ground Reference Point. Supply Voltage, 2.7 V to 5.25 V. Serial Interface Supply voltage, 2.7 V to 5 V. DVDD is independent of AVDD, therefore the serial interface can be operated at 3V with VDD at 5V or vice versa. Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose . It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin will go high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word informa-tion is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY pin is three-stated but the RDY bit remains active.
REV. PrD. Page 9 of 17
2
CS
3
AIN3(+)/P1
4
AIN3(-)/P2
5 6 7 8 9
AIN1(+) AIN1(-) AIN2(+) AIN2(-) REFIN(+)
10 11 12 13 14 15
REFIN(-) PSW GND AVDD DVDD DOUT/RDY
AD7798/AD7799
Pin No. 16 Mnemonic DIN
Preliminary Technical Data
Function Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers within the ADC, the register selection bits of the communications register identifying the appropriate register.
REV. PrD. Page 10 of 17
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
AD7798/AD7799
Figure 6.
Figure 9.
Figure 7.
Figure 10.
Figure 8.
Figure 11.
REV. PrD. Page 11 of 17
AD7798/AD7799 ON-CHIP REGISTERS
Preliminary Technical Data
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
CR7 WEN(0) CR6 R/W(0) CR5 RS2(0) CR4 RS1(0) CR3 RS0(0) CR2 CREAD(0) CR1 0(0) CR0 0(0)
Table 5. Communications Register Bit Designations
Bit Location CR7 Bit Name WEN Description Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the communications register. A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this position indicates that the next operation will be a read from the designated register. Register Address Bits. These address bits are used to select which of the ADC's registers are being selected during this serial interface communication. See Table 6. Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read, i.e., the contents of the data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The communications register does not have to be written to for data reads. To enable continuous read mode, the instruction 01011100 must be written to the communications register. To exit the continuous read mode, the instruction 01011000 must be written to the communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. These bits must be programmed to logic 0 for correct operation.
CR6 CR5-CR3 CR2
R/W RS2-RS0 CREAD
CR1-CR0
0
Table 6. Register Selection
RS2 0 0 0 0 0 1 1 1 1 RS1 0 0 0 1 1 0 0 1 1 RS0 0 0 1 0 1 0 1 0 1 Register Communications Register during a Write Operation Status Register during a Read Operation Mode Register Configuration Register Data Register ID Register IO Register Offset Register Full-Scale Register Register Size 8-Bit 8-Bit 16-Bit 16-Bit 24-Bit (AD7799) 16-bit (AD7798) 8-Bit 8-Bit 24-Bit (AD7799) 16-bit (AD7798) 24-Bit (AD7799) 16-Bit (AD7798)
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Preliminary Technical Data
STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; POWER-ON/RESET = 0x88)
AD7798/AD7799
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load bits RS2, RS1 and RS0 with 0. Table 7 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
SR7 RDY(1) SR6 ERR(0) SR5 NOREF(0) SR4 0(0) SR3 0/1 SR2 CH2(0) SR1 CH1(0) SR0 CH0(0)
Table 7. Status Register Bit Designations
Bit Location SR7 Bit Name RDY Description Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange, NOREF Cleared by a write operation to start a conversion. No Reference Bit. Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold. When set, conversion results are clamped to all ones. Cleared to indicate that a valid reference is applied between REFIN(+) and REFIN(-). The NOREF bit is enabled by setting the REF_DET bit in the Configuration register to 1. The ERR bit is also set if the voltage applied to the reference input is invalid. This bit is automatically cleared. This bit is automatically cleared on the AD7798, and is automatically set on the AD7799. These bits indicate which channel is being converted by the ADC.
SR6
ERR
SR5
NOREF
SR4 SR3 SR2-SR0
0 0/1 CH2-CH0
MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; POWER-ON/RESET = 0x000A)
The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to configure the Low Side Power Switch, select the mode of the ADC and select the ADC update rate. Table 8 outlines the bit designations for the mode register. MR0 through MR15 indicate the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit.
MR15 MD2(0) MR7 (0) MR14 MD1(0) MR6 (0) MR13 MD0(0) MR5 0(0) MR12 PSW(0) MR4 0(0) MR11 0(0) MR3 FS3(1) MR10 0(0) MR2 FS2(0) MR9 0(0) MR1 FS1(1) MR8 0(0) MR0 FS0(0)
Table 8. Mode Register Bit Designations
Bit Location MR15-MR13 MR12 Bit Name MD2-MD0 PSW Description Mode Select Bits. These bits select the operational mode of the AD7798/AD7799 (See Table 9). Power Switch Control Bit. Set by user to close the power switch PSW to GND. The power switch can sink up to 20 mA. Cleared by user to open the power switch. When the ADC is placed in power-down mode, the power switch is opened. These bits must be programmed with a Logic 0 for correct operation. Filter Update Rate Select Bits (see Table 10).
MR11-MR4 MR3-MR0
0 FS3-FS0
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AD7798/AD7799
Table 9. Operating Modes
MD2 0 MD1 0 MD0 0
Preliminary Technical Data
Mode Continuous Conversion Mode (Default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on, or following a write to the Mode, Configuration or IO Registers, a conversion is available after a period 2/ fADC while subsequent conversions are available at a frequency of fADC. Single Conversion Mode. In single conversion mode, the ADC is placed in power-down mode when conversions are not being performed. When single conversion mode is selected, the ADC powers up and performs a single conversion, which occurs after a period 2/fADC. The conversion result in placed in the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed. Idle Mode. In Idle Mode, the ADC Filter an Modulator are held in a reset state although the modulator clocks are still provided Power-Down Mode. In power down mode, all the AD7798/99 circuitry is powered down including the power switch and
0
0
1
0
1
0
0
1
1
burnout currents.
1 0 0 Internal Zero-Scale Calibration. An internal short is automatically connected to the enabled channel. A calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. Internal Full-Scale Calibration. The fullscale input is automatically connected to the selected analog input for this calibration. When the gain equals 1, a calibration takes 2 conversion cycles to complete. For higher gains, 4 conversion cycles are required for the fullscale calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale calibration coefficient is placed in the fullscale register of the selected channel. A fullscale calibration is required each time the gain of a channel is changed. The full-scale error of the AD7799/AD7798 is calibrated in the factory at both a gain of 1 and 128. These values are loaded into the fullscale register when the gain is 1 or 128. If a different PGA gain is used, then an Internal Full-Scale Calibration is required to calibrate out the gain error associated with that PGA gain. Note that Internal Fullscale Calibrations cannot be performed at a gain of 128. System Offset Calibration. User should connect the system zero-scale input to the channel input pins as selected by the CH2-CH0 bits. A system offset calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measurded offset calibration coefficient is placed in the offset register of the selected channel. System Full-Scale Calibration. User should connect the system full-scale input to the channel input pins s selected by the CH2-CH0 bits. A system full-scale calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale calibration coefficient is placed in the fullscale register of the selected channel.
1
0
1
1
1
0
1
1
1
REV. PrD. Page 14 of 17
Preliminary Technical Data
Table 10. Update Rates Available
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fADC (Hz) x 500 250 125 62.5 50 41.6 33.3 19.6 16.6 16.6 12.5 10 8.33 6.25 4.17 Tsettle (ms) x 5 8 16 32 40 48 60 101 120 120 160 200 240 320 480 Rejection @50 Hz/60 Hz
AD7798/AD7799
90 dB (60 Hz only) 84 dB (50 Hz only) 70 dB (50 Hz and 60 Hz) 67 dB (50 Hz and 60 Hz) 69 dB (50 Hz and 60 Hz) 73 dB (50 Hz and 60 Hz) 74 dB (50 Hz and 60 Hz) 75 dB @ 50/60 Hz
CONFIGURATION REGISTER (RS2, RS1, RS0 = 0, 1, 0; POWER-ON/RESET = 0x0710)
The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain and select the analog input channel. CON0 through CON15 indicate the bit locations, CON denoting the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
CON15 0 CON7 0 CON14 0 CON6 0 CON13 BO(0) CON5 REF_DET(0) CON12 U/B (0) CON4 BUF(1) CON11 0(0) CON3 0(0) CON10 G2(1) CON2 CH2(0) CON9 G1(1) CON1 CH1(0) CON8 G0(1) CON0 CH0(0)
Table 11. Configuration Register Bit Designations
Bit Location CON15-CON14 CON13 Bit Name 0 BO Description These bits must be programmed with a logic 0 for correct operation. Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer or In-Amp is active. Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 0x0000(00) output and a full-scale differential input will result in 0XFFFF(FF) output for the AD7798(99). Cleared by the user to enable bipolar coding. Negative full-scale differential input will result in an output code of 0x0000(00), zero differential input will result in an output code of 0x8000(00), and a positive full-scale differential input will result in an output code of 0xFFFF(FF) for the AD7798(99). This bit must be programmed with a Logic 0 for correct operation. Gain Select Bits. Written by the user to select the ADC input range as follows G2 G1 G0 Gain ADC Input Range (2.5V Reference) 0 0 0 0 0 1 1 (In-Amp not used) 2 (In-Amp not used) 2.5 V 1.25 V
CON12
U/B
CON11 CON10-CON8
0 G2-G0
REV. PrD. Page 15 of 17
AD7798/AD7799
Bit Location Bit Name Description 0 1 0 1 1 1 1 CON7-CON6 CON5 0 REF_DET 1 0 0 1 1 0 1 0 1 0 1 4 8 16 32 64 128
Preliminary Technical Information
625 mV 312.5 mV 156.2 mV 78.125 mV 39.06 mV 19.53 mV
CON4
BUF
CON3 CON2-CON0
0 CH2-CH0
These bits must be programmed to a logic 0 for correct operation. Enables the Reference Detect Function. When set, the NOREF bit in the status register indicates when the reference being used by the ADC is not present. When cleared, the reference detect function is disabled. Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. This bits must be programmed to a logic 0 for correct operation. Channel Select bits. Written by the user to select the active analog input channel to the ADC. CH2 CH1 CH0 Channel Calibration Pair 0 0 0 AIN1(+) - AIN1(-) 0 0 0 1 AIN2(+) - AIN2(-) 1 0 1 0 AIN3(+) - AIN3(-) 2 0 1 1 AIN1(-) - AIN1(-) 0 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 VDD Monitor
DATA REGISTER (RS2, RS1, RS0 = 0, 1, 1; POWER-ON/RESET = 0x0000 (AD7798)/ 0X000000 (AD7799))
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set.
ID REGISTER (RS2, RS1, RS0 = 1, 0, 0; POWER-ON/RESET = 0xX8 (AD7798)/ 0xX9 (AD7799))
The Identification Number for the AD7798/AD7799 is stored in the ID register. This is a read-only register.
IO REGISTER (RS2, RS1, RS0 = 1, 0, 1; POWER-ON/RESET = 0x00)
The I/O register is an 8-bit register from which data can be read or to which data can be written. IO0 through IO7 indicate the bit locations, IO denoting the bits are in the IO register. Table 12 outline the bit designations for the IO register. IO7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
IO7 0 IO6 IOEN(0) IO5 IO2DAT(0) IO4 IO1DAT(0) IO3 0 IO2 0 IO1 0 IO0 0
Table 12. I/O register Bit Designations
Bit Location IO7 IO6 Bit Name 0 IOEN Description These bits must be programmed to a logic 0 for correct operation. Configures the pins AIN3(+)/P1 and AIN3(-)/P2 as analog input pins or digital output pins. When this bit is set, the pins are configured as digital output pins P1 and P2. When this bit is cleared, these pins are configured as analog input pins AIN3(+) and AIN3(-). P2/P1 Data. These bits must be programmed to a logic 0 for correct operation.
REV. PrD. Page 16 of 17
IO5-IO4 IO3-IO0
IO2DAT/IO1DAT 0
Preliminary Technical Information
AD7798/AD7799
OFFSET REGISTER (RS2, RS1, RS0 = 1, 1, 0; Power-on/Reset = 0x8000 (AD7798)/0x800000 (AD7799))
The offset register holds the offset calibration coefficient for the ADC. The power-on-reset value of the internal zero-scale calibration coefficient register is 8000 hex (AD7798)/800000 hex (AD7799). The AD7798/AD7799 has 3 offset registers. Each of these registers is a 16/24-bit read/write register. However, when writing to the offset-scale registers, the ADC must be placed in power down mode or idle mode. This register is used in conjunction with its associated full-scale register to form a register pair. The power-on-reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user.
FULLSCALE Register (RS2, RS1, RS0 = 1, 1, 1; Power-on/Reset = 0x5XXX (AD7798)/0x5XXX000 (AD7799))
The full-scale register holds the full-scale calibration coefficient for the ADC. The AD7798/AD7799 has 3 full-scale registers. Each of these registers is a 16/24-bit read/write register. However, when writing to the full-scale registers, the ADC must be placed in power down mode or idle mode. The full-scale error of the AD7799/AD7798 is calibrated in the factory at both a gain of 1 and 128. Therefore if the gain is set to 128, as on power-on, or if the gain is set to 1, the factory calibrated internal full-scale coefficients are automatically loaded into the full-scale registers of the AD7799/AD7798. Therefore, every device will have different default coefficients. The user can overwrite these values, if required. These coefficients will be automatically overwritten if an internal or system full-scale calibration is initiated by the user. A full-scale calibration should be performed when the gain is changed. When the gain equals 128, internal full-scale calibrations cannot be performed.
TYPICAL APPLICATION
AVDD
GND REFIN(+)
IN+
AVDD AVDD
AD7799/AD7798
REFERENCE DETECT
AIN1(+)
OUTOUT+
AIN1(-)
IN-
AIN2(+) AIN2(-)
MUX
IN-AMP
SIGMA DELTA ADC
SERIAL INTERFACE AND CONTROL LOGIC
DOUT/RDY DIN SCLK CS
GND REFIN(-)
INTERNAL CLOCK
DVDD
PWRSW
Figure 12.
REV. PrD. Page 17 of 17
PR04856-0-6/04(PrD)

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